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[Communication] uart_verilog

Description: verilog & vhdl以及外国公司的应用说明。-Verilog
Platform: | Size: 148480 | Author: 丁路杰 | Hits:

[VHDL-FPGA-Verilog] FIR_1

Description: FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
Platform: | Size: 1024 | Author: 李甫 | Hits:

[VHDL-FPGA-Verilog] two_d_fir

Description: FIR FILTER verilog code-FIR FILTER Verilog code
Platform: | Size: 26624 | Author: QQ | Hits:

[Program doc] FIRVerilogHDL

Description: it is a fir filter program VerilogHDL.-it is a filter program VerilogHDL fir.
Platform: | Size: 4096 | Author: songzhigang | Hits:

[VHDL-FPGA-Verilog] fir2

Description: Verilog 编写的fir滤波器，可以实现fir滤波器的功能-Verilog prepared by the fir filter can achieve fir filter function
Platform: | Size: 12288 | Author: 宋南 | Hits:

[VHDL-FPGA-Verilog] Fir

Description: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 1024 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] fir

Description: 完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位，输出数据宽度为16位。 3、 滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.
Platform: | Size: 5120 | Author: fredyu | Hits:

[VHDL-FPGA-Verilog] 8stepSymmetryCoefficientFilter

Description: 8阶对称系数并行FIR滤波器(verilog)用作数字滤波，系数可调。根据实际截止频率决定。-8-order FIR filter symmetric coefficients parallel (verilog) used for digital filtering, adjustable coefficient. Decisions based on the actual cut-off frequency.
Platform: | Size: 1024 | Author: TGY | Hits:

[VHDL-FPGA-Verilog] fir

Description: Verilog 程序， 实现4阶 fir-filter滤波器。 -Verilog procedures, to achieve 4-order filter fir-filter.
Platform: | Size: 1024 | Author: 左麟 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Platform: | Size: 909312 | Author: 王志 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: ＦＰＧＡ实现数字滤波器，基于硬件描述语言ＶＥＲＩＬＯＧ　ＨＤＬ，顶层文件ＦＩＲ．Ｖ-FPGA realization of digital filters, based on the hardware description language VERILOG HDL, the top-level file FIR. V
Platform: | Size: 5120 | Author: YP | Hits:

[Documents] fir

Description: 线性相位FIR滤波器（17阶）的VHDL语言设计 功能很强大，很好用-Linear phase FIR filter (17 bands) of the VHDL language design features a very powerful, very good use
Platform: | Size: 148480 | Author: jingjing | Hits:

[Other] FIR

Description: This implementation of Low power Finite Impulse response filter design and implemented in Verilog-This is implementation of Low power Finite Impulse response filter design and implemented in Verilog
Platform: | Size: 5120 | Author: Ravindra | Hits:

[VHDL-FPGA-Verilog] fir

Description: 用状态机编写的FIR，verilog代码，已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
Platform: | Size: 1024 | Author: 于水洋 | Hits:

[VHDL-FPGA-Verilog] fir

Description: fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand
Platform: | Size: 2048 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] fir

Description: Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
Platform: | Size: 1024 | Author: lifei | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[VHDL-FPGA-Verilog] fir

Description: 比较简单的16位fir滤波器，16阶，Verilog编写-Simple 16-bit fir filter, 16 bands, Verilog prepared
Platform: | Size: 2048 | Author: 刘安 | Hits:

[VHDL-FPGA-Verilog] fir filter design

Description: FIR FILTER DESIGN IN VERILOG ON FPGA
Platform: | Size: 18432 | Author: GIRISH | Hits:

[Other] 基于FPGA和IP核的FIR低通滤波器

Description: 用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
Platform: | Size: 39936 | Author: 曾今的1994 | Hits:
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